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Espressif Systems /ESP32-S3 /TIMG0 /RTCCALICFG

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Interpret as RTCCALICFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RTC_CALI_START_CYCLING)RTC_CALI_START_CYCLING 0RTC_CALI_CLK_SEL 0 (RTC_CALI_RDY)RTC_CALI_RDY 0RTC_CALI_MAX0 (RTC_CALI_START)RTC_CALI_START

Description

RTC calibration configure register

Fields

RTC_CALI_START_CYCLING

Reserved
RTC_CALI_CLK_SEL

0:rtc slow clock. 1:clk_80m. 2:xtal_32k.
RTC_CALI_RDY

Reserved
RTC_CALI_MAX

Reserved
RTC_CALI_START

Reserved

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data